The present invention relates to radio communications, and more particularly, to synchronization and DC-offset compensation in frequency modulation (FM) radio transceivers.
An FM signal is typically demodulated by multiplying the FM signal by its time derivative. This is due to the fact that the resulting product amplitude is proportional to both the amplitude and the angular frequency of the FM signal, the angular frequency including both an intermediate frequency (IF) and an induced FM frequency deviation. Thus, when the FM signal is made to have a constant amplitude envelope (e.g., when the FM signal is processed using an automatic gain control, or AGC, processor or a hard limiter), the resulting product signal has an amplitude which is proportional to the angular frequency alone, and the modulation signal of interest can be recovered by using a low-pass filter to remove signal components at multiples of the IF frequency.
This concept is shown in FIG. 1, wherein an FM transmission system 100 is shown to include a frequency modulation processor 105 and a frequency demodulation processor including a time derivative processor 110, a mixer 120 and a low-pass filter 130. In FIG. 1, a baseband signal of interest (e.g., a digital voice or other data waveform in which a high voltage level represents a logical 1 and a low voltage level represents a logical 0) is coupled to an input of the frequency modulation processor 105, and the frequency modulation processor 105 provides an FM output signal for transmission (e.g., across the air interface) to the frequency demodulation processor.
Within the frequency demodulation processor, a constant envelope FM signal is coupled to an input of the time derivative processor 110 and to a first input of the mixer 120. Further, an output of the time derivative processor 110 is coupled to a second input of the mixer 120, and an output of the mixer is coupled to an input of the low-pass filter 130. An output of the low-pass filter represents a recovered version of the baseband signal of interest. Those of skill in the art will appreciate that the below described functionality of the components of FIG. 1 can be implemented using known hardware techniques.
On the FM transmitter side, the frequency modulation processor 105 uses the baseband signal to modulate the frequency of an IF carrier, for example using some form of frequency shift keying (e.g., Gaussian frequency shift keying or GFSK). The resulting FM output signal is then typically upconverted to a designated portion of the available radio spectrum before transmission. On the FM receiver side, the received FM signal is downconverted and hard limited to provide the constant envelope FM input signal. The time derivative processor 110 then dynamically computes the instantaneous time derivative of the FM input signal, and the mixer 120 multiplies the instantaneous time derivative of the FM input signal with the FM input signal itself. As noted above, the output of the mixer 120 is thus proportional to the angular frequency of the FM input signal, including the IF carrier and the induced FM frequency deviation. The low-pass filter 130 then removes multiples of the IF carrier to recover the baseband signal.
In practice, an FM detector (e.g., the combination of the time derivative processor 110 and the mixer 120 of FIG. 1) must include accurate delay elements or filters with well controlled phase characteristics to generate the time-derivative approximation. Otherwise, excessive DC offset can be introduced into the detected signal, such DC offset potentially disrupting successful synchronization and detection of the baseband signal of interest. Moreover, improper tuning of an IF filter (e.g., the low-pass filter 130 of FIG. 1), as well as inaccuracies in the local reference oscillator (LO) used to generate the IF frequency at the transmitting and/or the receiving side, can also introduce significant DC offset in the recovered baseband signal. Although the reference oscillators and the passive resonator components used to implement FM detectors and IF filters can be trimmed at production time, these components are subject to detuning with time and with varying operating conditions, and DC offsets in the recovered signal can nonetheless be a problem.
Consequently, FM receivers are typically designed to dynamically compensate for DC offset. Advantageously, such dynamic skewing of the output of an IF strip (i.e., an FM detector and an IF filter) compensates for local and remote reference frequency differences, as well as detuning of passive resonator components, and thus improves overall FM receiver sensitivity. In conventional DC-offset compensation schemes, at least a portion of the FM signal (e.g., the preamble of a digital data packet) is designed to have zero mean (e.g., an equal number of logical 1""s and 0""s). Doing so permits a relatively simple analog circuit to be used for obtaining a dynamic estimate of the prevailing DC-offset at an FM receiver. However, known methods for providing and utilizing a zeromean signal for DC-offset compensation and FM receiver synchronization add significant overhead to the baseband signal being transmitted. In applications where speed is critical, such signal overhead can be prohibitive. Consequently, there is a need for improved methods and apparatus for providing DC-offset compensation and signal synchronization in FM communications systems.
The present invention fulfills the above-described and other needs by providing a multi-part digital preamble for use in transmitting digital data packets. Advantageously, a preamble according to the invention substantially reduces the overall length of DC-free sequences that are transmitted with each data packet in a digital FM system. According to exemplary embodiments, a multi-part preamble includes a short, substantially DC-free leading part which enables coarse estimation of a prevailing DC level at an FM receiver. The exemplary preamble also includes a synchronization part which is not necessarily substantially DC-free and which carries timing and/or other useful information (e.g., channel identification, destination address, etc.) that can vary from data packet to data packet (e.g., depending on sender, recipient, time of day, etc.). According to the invention, the synchronization word is protected by code to reduce false detection probability and can therefore be successfully detected using only the coarse DC-offset correction provided by the short leading portion of the preamble.
Following the synchronization part, or within the synchronization part itself, the exemplary multi-part preamble includes one or more substantially DC-free trailing parts that can be used to perform final DC-offset estimation and compensation. Since signal timing is well known after the synchronization part is detected, the substantially DC-free trailing part(s) can be made extremely short. Moreover, since the substantially DC-free leading and trailing parts are short, and since the synchronization part carries useful information which can be different for each data packet, the overhead associated with a digital data packet preamble according to the invention is significantly reduced as compared to conventional digital data packet preambles.
An exemplary radio transmitter according to the invention includes a modulator transmitting a succession of digital data packets by modulation of a carrier signal. In the embodiment, the modulator provides a digital preamble for each transmitted digital data packet, and each digital preamble includes a synchronization part and at least two substantially DC-free parts. For example, each digital preamble can include a substantially DC-free leading part, a synchronization part, and one or more substantially DC-free trailing parts.
An exemplary radio receiver according to the invention includes a detector receiving and demodulating a succession of digital data packets (each digital data packet including a digital preamble, and each digital preamble including a synchronization part and at least two substantially DC-free parts), and an estimation and synchronization processor estimating and removing a DC offset from an output of the detector and synchronizing the output of the detector. In the embodiment, the processor provides a coarse estimate of the DC offset for each digital data packet based on one of the substantially DC-free parts of the data packet preamble and synchronizes each digital data packet based on the synchronization part of the data packet preamble once the coarse estimate for the data packet is established. Further, the processor provides a fine estimate of the DC offset for each digital data packet based on another of the substantially DC-free parts of the data packet preamble once synchronization for the data packet is established. Each digital preamble can include, for example, a substantially DC-free leading part, a synchronization part, and one or more substantially DC-free trailing parts.